The problem of mapping complex deep neural network (DNN) computational graphs onto systolic arrays is not easy as moving memory data outside the chip can lead to energy consumption; the conventional High-Level Synthesis (HLS) tools rely on the user-specified pragmas and fusion rules heuristically. In order to overcome this, the authors developed an advanced reinforcement learning (RL)-guided HLS framework (RL-HLS) based on graphs; this solution is capable of performing both horizontal and vertical operation fusion and defining microarchitectural HLS rules in accordance with the constraints set on energy, latency, and Field-Programmable Gate Array (FPGA) resources. To achieve this goal, the authors implemented a Graph Isomorphism Network (GIN) algorithm to describe the states of graphs; then, they used a hierarchical Proximal Policy Optimization (PPO) policy to investigate the design space. According to the results obtained from trial runs with General Matrix Multiplication (GEMM), ResNet-18, ResNet-50, MobileNetV3, and Vision Transformer (ViT) patch-embedding tasks, the authors managed to cut the power consumption by 82.7% on average, reduce the latency by 89.9%, and increase Processing Element (PE) utilization from 7.4% to 69%.